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ai02115 16 a0-a15 w dq0-dq15 v cc M29F105B e v ss 16 g figure 1. logic diagram M29F105B 1 mbit (64kb x16, block erase) single supply flash memory 5v 10% supply voltage for program, erase and read operations fast access time: 55ns fast programming time: 10 m s typical program/erase controller (p/e.c.) program word-by-word status register bits memory blocks boot block (bottom location) parameter and main blocks block, multi-block and chip erase multi-block protection/temporary unprotection modes erase suspend and resume modes read and program another block during erase suspend low power consumption stand-by and automatic stand-by 100,000 program/erase cycles per block electronic signature manufacturer code: 0020h device code: 0087h may 1998 1/28 a0-a15 address inputs dq0-dq7 data input/outputs, command inputs dq8-dq15 data input/outputs e chip enable g output enable w write enable v cc supply voltage v ss ground table 1. signal names tsop40 (n) 10 x 14mm
symbol parameter value unit t a ambient operating temperature (3) 40 to 85 c t bias temperature under bias 50 to 125 c t stg storage temperature 65 to 150 c v io (2) input or output voltages 0.6 to 7 v v cc supply voltage 0.6 to 7 v v (a9, e, g) (2) a9, e, g voltage 0.6 to 13.5 v notes: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not i mplied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. 2. minimum voltage may undershoot to 2v during transition and for less than 20ns. 3. depends on range. table 2. absolute maximum ratings (1) dq15 dq12 dq11 a13 v cc nc nc w a5 dq0 a2 a1 dq4 a6 a0 dq8 dq1 dq6 dq10 dq9 v ss dq7 dq5 a7 a8 a10 a12 a9 v ss a11 ai02116 M29F105B 10 1 11 20 21 30 31 40 e a4 a3 dq2 dq3 a15 a14 dq14 dq13 g figure 2. tsop pin connections warning: nc = not connected. description the M29F105B is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a word-by-word basis using only a single 5v v cc supply. word program- ming takes typically 20 m s. for program and erase operations the necessary high voltages are gener- ated internally. the device can also be pro- grammed in standard programmers. the array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. blocks can be protected against pro- graming and erase on programming equipment and in the application.they can also be temporarily unprotected. each block can be programmed and erased over 100,000 cycles. block erase is performed in typically 1.0 second for the main blocks. instructions for read/reset, auto select for read- ing the electronic signature or block protection status, programming, block and chip erase, erase suspend and resume block protect and blocks unprotect are written to the device in cycles of commands to a command interface using stand- ard microprocessor write timings. the device is offered in tsop40 (10 x 14mm) packages. organisation the M29F105B is organised as 64k x16 bits. the memory uses the address inputs a0-a15 and the data input/outputsdq0-dq15. memory control is provided by chip enable e, output enable g and write enable w inputs. 2/28 M29F105B
ai02117 M29F105B 8k word boot block 4k word parameter block 4k word parameter block 16k word main block 32k word main block ffffh 8000h 7fffh 4000h 3fffh 2000h 1fffh 0000h 3000h 2fffh figure 3. memory map and block address table address range a15 a14 a13 a12 0000h-1fffh 0 0 0 x 2000h-2fffh 0 0 1 0 3000h-3fffh 0 0 1 1 4000h-7fffh 0 1 x x 8000h-ffffh 1 x x x table 3. M29F105B block address table erase and program operations are controlled by an internal program/erase controller (p/e.c.). status register data output on dq7 provides a data poll- ing signal, and dq6 and dq2 provide toggle signals to indicate the state of the p/e.c opera- tions. memory blocks the devices feature asymmetrically blocked archi- tecture providing system memory integration. the M29F105B device has an array of 5 blocks, one boot block of 8k words, two parameter blocks of 4k words, one main block of 16k words and one main blocks of 32k words. the M29F105B locates the boot block starting at the bottom of the memory address space. the memory map is shown in figure 3. each block can be erased separately, any combination of blocks can be specified for multi- block erase or the entire chip may be erased. the erase operations are managed automatically by the p/e.c. the block erase operation can be sus- pended in order to read from or program to any block not being erased, and then resumed. block protection provides additional data security. each block can be separately protected or unprotected against program or erase on programming equip- ment. bus operations the following operations can be performed using the appropriatebus cycles: read (array, electronic signature, block protection status), write com- mand, output disable, standby, reset, block pro- tection, unprotection, protection verify and unprotection verify. see tables. command interface instructions, made up of commands written in cy- cles, can be given to the program/erasecontroller through a command interface (c.i.). for added data protection, program or erase execution starts after 4 or 6 cycles. the first, second, fourth and fifth cycles are used to input coded cycles to the c.i. this coded sequence is the same for all pro- gram/erase controller instructions. the 'com- mand' itself and its confirmation, when applicable, are given on the third, fourth or sixth cycles. any incorrect command or any improper command se- quence will reset the device to read array mode. 3/28 M29F105B
instructions ten instructions are definedto perform read array, auto select (to read the electronic signature or block protection status), program, block protect, blocks unprotect, block erase, chip erase, erase suspend and erase resume. the internal p/e.c. automatically handles all timing and verification of the program and erase operations. the status register data polling, toggle and error bits may be read at any time, during programming or erase, to monitor the progress of the operation. instructions are composed of up to six cycles. the first two cycles input a coded sequence to the command interfacewhich iscommon to all instruc- tions (see table 9). the third cycle inputs the instruction set-up command. subsequent cycles output the addressed data, electronic signature or block protection status for read operations. in order to give additional data protection,the instruc- tions for program and block or chip erase require further command inputs. for a programinstruction, the fourth command cycle inputs the address and data to be programmed. for an erase instruction (block or chip), the fourth and fifth cycles input a further coded sequence before the command con- firmation on the sixth cycle. erasure of a memory block may be suspended,in orderto read data from another block or to program data in another block, and then resumed. the block protect and blocks unprotect com- mands allow these operations to be performed in the application. they provide a six cycle command access of the equivalent bus operations. this en- ables updates of the memory protected blocks in the field, without the use of a programmer or the need to generate 12v on the application. when power is first applied or if v cc falls below v lko , the command interface is reset to read array. signal descriptions see figure 1 and table 1. address inputs (a0-a15) . the address inputs for the memory array are latched during a write opera- tion on the falling edge of chip enable e or write enable w. when a9 is raised to v id , either a read electronicsignature manufactureror device code, block protection status or a write block protection or block unprotection is enabled depending on the combination of levels on a0, a1 a6, a12 and a15. data input/outputs (dq0-dq15). the input is data to be programmed in the memory array or a command to be written to the c.i. both are latched on the rising edge of chip enablee or write enable w. the output is data from the memory array, the electronic signature manufacturer or device codes, the block protection status or the status register data polling bit dq7, the toggle bits dq6 and dq2, the error bit dq5 or the erase timer bit dq3. outputs are valid when chip enable e and output enable g are active. the output is high impedance when the chip is deselected or the outputs are disabled and when rpnc is at a low level. chip enable (e). the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. e high deselectsthe memory and reduces the power consumptionto the standby level. e can also be used to control writing to the command register and to the memory array, while w remains at a low level. the chip enable must be forced to v id during the block unprotection opera- tion. output enable (g). the output enable gates the outputs through the data buffers during a read operation. when g is high the outputs are high impedance. g must be forced to v id level during block protection and unprotection operations. write enable (w). this input controls writing to the command registerand addressand datalatches. v cc supply voltage. the power supply for all operations (read, program and erase). v ss ground. v ss is the reference for all voltage measurements. device operations see tables 4, 5 and 6. read. read operations are used to output the contents of the memory array, the electronic sig- nature, the status register or the block protection status. both chip enable e and output enable g must be low in order to read the output of the memory. write. write operations are used to give instruction commands to the memory or to latch input data to be programmed. a write operation is initiated when chip enable e is low and write enable w is low with output enable g high. addresses are latched on the falling edge of w or e whichever occurs last. commands and input dataare latchedon therising edge of w or e whichever occurs first. output disable. the data outputs are high imped- ance when the output enable g is high with write enable w high. standby. the memory is in standby when chip enable e is high and the p/e.c. is idle. the power consumption is reduced to the standby level and the outputs are high impedance, independent of the output enable g or write enable w inputs. 4/28 M29F105B
operation e g w a0 a1 a6 a9 a12 a15 dq0-dq15 read word v il v il v ih a0 a1 a6 a9 a12 a15 data output write word v il v ih v il a0 a1 a6 a9 a12 a15 data input output disable v il v ih v ih xxxxxx hi-z standby v ih x x xxxxxx hi-z reset x x x x x x x x x hi-z block protection (2) v il v id v il pulse x x x v id xx x blocks unprotection v id v id v il pulse x x x v id v ih v ih x block protection verify (2,4) v il v il v ih v il v ih v il v id a12 a15 block protect status (3) block unprotection verify (2,4) v il v il v ih v il v ih v ih v id a12 a15 block protect status (3) notes: 1. x = v il or v ih 2. block address must be given on a12-a15 bits. 3. see table 6. 4. operation performed on programming equipment. table 4. user bus operations (1) code e g w a0 a1 other addresses dq8-dq15 dq0-dq7 manufact. code v il v il v ih v il v il don't care 00h 20h device code v il v il v ih v ih v il don't care 00h 87h table 5. read electronic signature (following as instruction or with a9 = v id ) code e g w a0 a1 a12-a15 other addresses dq0-dq7 protected block v il v il v ih v il v ih block address don't care 01h unprotected block v il v il v ih v il v ih block address don't care 00h table 6. read block protection with as instruction automatic standby. after 150ns of bus inactivity and when cmos levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumptionis reduced to the cmos standby value, while outputs still drive the bus. electronic signature. two codes identifying the manufacturer and the device can be read from the memory. the manufacturer's code for stmi- croelectronics is 20h,the device code is 87h. these codes allow programming equipment or applica- tions to automatically match their interface to the characteristics of the M29F105B. the electronic signature is output by a read operation when the voltage applied to a9 is at v id and address inputs a1 is low. the manufacturer code is output when the address input a0 is low and the device code when this input is high. other address inputs are ignored. the codes are output on dq0-dq7. this is shown in table 4. the electronic signature can also be read, without raising a9 to v id , by giving the memory the instruc- tion as. the codes are output on dq0-dq7 with dq8-dq15 at 00h. 5/28 M29F105B
block protection. each block can be separately protected against program or erase on program- ming equipment. block protection provides addi- tional data security, as it disables all program or erase operations.this mode is activatedwhen both a9 and g are raised to v id and an address in the block is applied on a12-a15. the block protection algorithm is shown in figure 14. block protection is initiated on the edge of w falling to v il . then after a delay of 100 m s, the edge of w rising to v ih ends the protection operations. block protection verify is achieved by bringing g, e, a0 and a6 to v il and a1 to v ih , while w is at v ih and a9 at v id . underthese conditions, reading the data output will yield 01h if the block defined by the inputs on a12-a15 is protected. any attempt to program or erase a pro- tected block will be ignored by the device. the blocks can also be protected without the use of v id , by giving to the memory the instruction bp (see table 9). block unprotection. all protected blocks can be unprotected on programming equipment to allow updating of bit contents. all blocks must first be protected before the unprotection operation. block unprotection is activated when a9, g and e are at v id and a12, a15 at v ih . the block unprotection algorithm is shown in figure 15. unprotection is initiated by the edge of w falling to v il . aftera delay of 10ms, the unprotection operation will end. un- protectionverify is achieved by bringing g and e to v il while a0 is at v il , a6 and a1 are at v ih and a9 remains at v id . in these conditions, reading the output data will yield 00h if the block defined by the inputs a12- a15 has been succesfully unprotected. each block must be separately verified by giving its address in order to ensure that it has been unpro- tected. the blocks can also be unprotectedwithout the use of v id , by giving to the memory the instruc- tion bu (see table 9). instructions and commands the command interface latches commands writ- ten to the memory. instructions are made up from one or more commands to perform read memory array, read electronic signature, read block pro- tection, program, block protect, blocks unprotect, block erase, chip erase, erase suspend and erase resume. commands are made of address and data sequences. the instructions require from 1 to 6 cycles, the first or first three of which are always write operations used to initiate the instruc- tion. they are followed by either further writecycles to confirm the first command or execute the com- mand immediately. command sequencingmust be followed exactly. any invalid combination of com- mands will reset the device to read array. the increased number of cycles has been chosen to assure maximum data security. instructions are initialised by two initial coded cycles which unlock the command interface. in addition, for erase, instruction confirmation is again preceded by the two coded cycles. status register bits p/e.c. status is indicated during execution by data polling on dq7, detection of toggle on dq6 and dq2, or error on dq5 and erase timer dq3 bits. any read attempt during program or erase com- mand executionwill automaticallyoutput these five status register bits. the p/e.c. automatically sets bits dq2, dq3, dq5, dq6 and dq7. other bits (dq0, dq1 and dq4) are reserved for future use and should be masked. see tables 8 and 10. data polling bit (dq7). when programming op- erations are in progress, this bit outputs the com- plement of the bit being programmed on dq7. during erase operation, it outputs a '0'. after com- pletion of the operation, dq7 will output the bit last programmed or a '1' after erasing. data polling is valid and only effective during p/e.c. operation, that is after the fourth w pulse for programming or after the sixth w pulse for erase. it must be per- formed at the address being programmed or at an address within the block being erased. if all the blocks selected for erasure are protected, dq7 will be set to '0' for about 100 m s, and then return to the previous addressed memory data value. see fig- ure 11 for the data polling flowchart and figure 10 for the data polling waveforms. dq7 will also flag the erase suspend mode by switching from '0' to '1' at the start of the erase suspend. in order to monitor dq7 in the erase suspend mode an ad- dress within a block being erased must be pro- vided. for a read operation in erase suspend mode, dq7 will output '1' if the read is attempted on a blockbeing erasedand the data valueon other blocks. during program operation in erase sus- pend mode, dq7 will have the same behaviour as in the normal program execution outside of the suspend mode. toggle bit (dq6). when programming or erasing operations are in progress, successive attempts to read dq6 will output complementarydata. dq6 will toggle following toggling of either g, or e when g is low. the operation is completed when two suc- cessive reads yield the same output data. the next read will output the bit last programmed or a '1' after erasing. the toggle bit dq6 is valid only during p/e.c. operations, that is after the fourth w pulse for programming or after the sixth w pulse for erase. if the blocks selected for erasure are pro- tected, dq6 will toggle for about 100 m s and then return back to read. dq6 will be set to '1' if a read 6/28 M29F105B
operationis attemptedon an erase suspendblock. when erase is suspended dq6 will toggle during programming operations in a block different to the block in erase suspend. either e or g toggling will cause dq6 to toggle. see figure 12 for toggle bit flowchart and figure 13 for toggle bit waveforms. toggle bit (dq2). this toggle bit, together with dq6, can be used to determine the device status during the erase operations. it can also be used to identify the block being erased. during erase or erase suspend a read from a block being erased will cause dq2 to toggle. a read from a block not being erased will set dq2 to '1' during erase and to dq2 during erase suspend. during chip erase a read operation will cause dq2 to toggle as all blocks are being erased. dq2 will be set to '1' during program operation and when erase is com- plete. after erase completion and if the error bit dq5 is set to '1', dq2 will toggle if the faulty block is addressed. error bit (dq5). this bit is set to '1' by the p/e.c. when there is a failure of programming, block erase, or chip erase that results in invalid data in the memory block. in caseof an error in block erase or program, the block in which the error occured or to which the programmed data belongs, must be discarded. the dq5 failure condition will also ap- pear if a user tries to program a '1' to a locationthat is previously programmed to '0'. other blocks may stillbe used.the error bit resets after a read/reset (rd) instruction. in case of success of program or erase, the error bit will be set to '0' . erase timer bit (dq3). this bit is set to '0' by the p/e.c. when the last block erase command has been entered to the command interface and it is awaiting the erase start. when the wait period is finished, after 50 m s to 120 m s, dq3 returns to '1'. coded cycles the two coded cycles unlock the command inter- face. they are followed by an input command or a confirmation command. the coded cycles consist of writing the data aah at address 555h during the first cycle. during the second cycle the coded cycles consist of writing the data 55h at address aaah. address lines a0 to a11 are valid other address lines are 'don't care'. the coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles. instructions see table 9. read/reset (rd) instruction. the read/reset instruction consists of one write cycle giving the command f0h. it can be optionallypreceded by the two coded cycles. subsequentread operationswill read the memory array addressed and output the data read. a wait state of 10 m s is necessary after read/reset prior to any valid read if the memory was in an erase mode when the rd instruction is given. auto select (as) instruction. this instruction uses the two coded cycles followed by one write cycle giving the command 90h to address 555h for command set-up. a subsequentread will output the manufacturer code and the device code or the block protection status depending on the levels of a0 and a1. the manufacturer code, 20h, is output when the addresses lines a0 and a1 are low, the device code, 87h is output when a0 is high with a1 low. the as instruction also allows access to the block protectionstatus. after givingthe as instruction,a0 and a6 are set to v il with a1 at v ih , while a12-a15 define the address of the block to be verified. aread in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. mode dq7 dq6 dq2 program dq7 toggle 1 erase 0 toggle note 1 erase suspend read (in erase suspend block) 1 1 toggle erase suspend read (outside erase suspend block) dq7 dq6 dq2 erase suspend program dq7 toggle n/a note: 1. toggle if the address is within a block being erased. '1' if the address is within a block not being erased. table 8. polling and toggle bits hex code command 00h invalid/reserved 10h chip erase confirm 20h reserved 30h block erase resume/confirm 80h set-up erase 90h read electronic signature/ block protection status a0h program b0h erase suspend f0h read array/reset table 7. commands 7/28 M29F105B
mne. instr. cyc. 1st cyc. 2nd cyc. 3rd cyc. 4th cyc. 5th cyc. 6th cyc. 7th cyc. rd (2,4) read/reset memory array 1+ addr. (3,7) x read memory array until a new write cycle is initiated. data f0h 3+ addr. (3,7) 555h aaah 555h read memory array until a new write cycle is initiated. data aah 55h f0h as (4) auto select 3+ addr. (3,7) 555h aaah 555h read electronic signature or block protection status until a new write cycle is initiated. see note 5 and 6. data aah 55h 90h pg program 4 addr. (3,7) 555h aaah 555h program address read data polling or toggle bit until program completes. data aah 55h a0h program data bp block protect 6 addr. (3,7) 555h aaah 555h 555h aaah block address (11) data aah 55h 80h aah 55h 40h bu blocks unprotect 6 addr. (3,7) 555h aaah 555h 555h aaah 9041h data aah 55h 80h aah 55h 60h be block erase 6 addr. (3,7) 555h aaah 555h 555h aaah block address additional block (8) data aah 55h 80h aah 55h 30h 30h ce chip erase 6 addr. (3,7) 555h aaah 555h 555h aaah 555h note 9 data aah 55h 80h aah 55h 10h es (10) erase suspend 1 addr. (3,7) x read until toggle stops, then read all the data needed from any block(s) not being erased then resume erase. data b0h er erase resume 1 addr. (3,7) x read data polling or toggle bits until erase completes or erase is suspended another time data 30h notes: 1. commands not interpreted in this table will default to read array mode. 2. a wait of 10 m s is necessary after a read/reset command if the memory was in an erase or erase suspend mode before starting any new operation. 3. x = don't care. 4. the first cycles of the rd or as instructions are followed by read operations. any number of read cycles can occur after the command cycles. 5. signature address bits a0, a1, at v il will output manufacturer code (20h). address bits a0 at v ih and a1, at v il will output device code. 6. block protection address: a0, at v il ,a1atv ih and a12-a15 within the block will output the block protection status. 7. for coded cycles address inputs a12-a15 are don't care. 8. optional, additional blocks addresses must be entered within a 50 m s delay after last write entry, timeout status can be verified through dq3 value. when full command is entered, read data polling or toggle bit until erase is completed or suspended. 9. read data polling, toggle bits until erase completes. 10.during erase suspend, read and data program functions are allowed in blocks not being erased. 11.block address must be given on a12-a15 while a6 and a1 are set to v il , and a0 is set to v ih . table 9. instructions (1) 8/28 M29F105B
dq name logic level definition note 7 data polling '1' erase complete or erase block in erase suspend indicates the p/e.c. status, check during program or erase, and on completion before checking bits dq5 for program or erase success. '0' erase on-going dq program complete or data of non erase block during erase suspend dq program on-going 6 toggle bit '-1-0-1-0-1-0-1-' erase or program on-going successive reads output complementary data on dq6 while programming or erase operations are on-going. dq6 remains at constant level when p/e.c. operations are completed or erase suspend is acknowledged. dq program complete '-1-1-1-1-1-1-1-' erase complete or erase suspend on currently addressed block 5 error bit '1' program or erase error this bit is set to '1' in the case of programming or erase failure. '0' program or erase on-going 4 reserved 3 erase time bit '1' erase timeout period expired p/e.c. erase operation has started. only possible command entry is erase suspend (es). '0' erase timeout period on-going an additional block to be erased in parallel can be entered to the p/e.c. 2 toggle bit '-1-0-1-0-1-0-1-' chip erase, erase or erase suspend on the currently addressed block. erase error due to the currently addressed block (when dq5 = '1'). indicates the erase status and allows to identify the erased block 1 program on-going, erase on-going on another block or erase complete dq erase suspend read on non erase suspend block 1 reserved 0 reserved notes: logic level '1' is high, '0' is low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. table 10. status register bits program (pg) instruction. this instruction uses four write cycles. the program command a0h is written to address 555h on the third cycle after two coded cycles. a fourth write operation latches the address on the falling edge of w or e and the data to be written on the rising edge and starts the p/e.c. read operationsoutput the status register bits after the programming has started. memory programming is made only by writing '0' in place of '1'. status bits dq6 and dq7 determine if program- ming is on-goingand dq5 allows verification of any possible error. programming at an address not in blocks being erased is also possible during erase suspend. in this case, dq2 will toggle at the ad- dress being programmed. 9/28 M29F105B
ai01275b 3v high speed 0v 1.5v 2.4v standard 0.45v 2.0v 0.8v figure 4. ac testing input output waveform ai01276b 1.3v out c l c l = 30pf for high speed c l = 100pf for standard c l includes jig capacitance 3.3k w 1n914 device under test figure 5. ac testing load circuit symbol parameter test condition min max unit c in input capacitance v in =0v 6 pf c out output capacitance v out =0v 12 pf note: 1. sampled only, not 100% tested. table 12. capacitance (1) (t a =25 c, f = 1 mhz ) block protect (bp) instruction . this instruction uses six write cycles. the set-up command 80h is written to address 555h on the third cycle after the two coded cycles. the block protect confirm com- mand 40h is similarly written on the sixth cycle after another two coded cycles. during the input of the second command an address with a0 at v ih ,a1 and a6 at v il , and within the block to be protected is given and latched into the memory. the block protection algorithm flowchart is described in fig- ure 16. blocks unprotect (bu) instruction . this instruc- tion uses six write cycles. the set-up command 80h is written to address 555h on the third cycle after the two coded cycles. the block unprotect confirm command 60h is similarly written to ad- dress 9041h after another two coded cycles. the blocks unprotection alghrithm flowchart is de- scribed in figure 17. block erase (be) instruction . this instruction uses a minimum of six write cycles. the set-up command 80h is written to address 555h on third cycle after the two coded cycles. the block erase confirm command 30h is similarly written on the sixth cycle after another two coded cycles. during the input of the secondcommand an addresswithin the block to be erased is given and latched into the memory. additional block erase confirm com- high speed standard input rise and fall times 10ns 10ns input pulse voltages 0 to 3v 0.45v to 2.4v input and output timing ref. voltages 1.5v 0.8v to 2v table 11. ac measurement conditions 10/28 M29F105B
symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 m a i lo output leakage current 0v v out v cc 1 m a i cc1 supply current (read) ttl e = v il ,g=v ih , f = 6mhz 50 ma i cc2 supply current (standby) ttl e = v ih 1ma i cc3 supply current (standby) cmos e = v cc 0.2v 100 m a i cc4 supply current (program or erase) byte program, block or chip erase in progress 20 ma v il input low voltage 0.5 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 5.8ma 0.45 v v oh output high voltage ttl i oh = 2.5ma 2.4 v output high voltage cmos i oh = 100 m av cc 0.4v v i oh = 2.5ma 0.85 v cc v v id a9, e, g voltage 11.5 12.5 v i id a9, e, g current a9 = v id 100 m a v lko supply voltage (erase and program lock-out) 3.2 4.2 v table 13. dc characteristics (t a = 0 to 70 c or 40 to 85 c; v cc =5v 10%) mands and block addresses can be written sub- sequently to erase other blocks in parallel, without further coded cycles. the erase will start after an erase timeout period of 80 m s. thus, additional erase confirm commands for other blocks must be given within this delay. the input of a new erase confirm command will restart the timeout period. the status of the internal timer can be monitored through the level of dq3, if dq3 is '0' the block erase command has been given and the timeout is running, if dq3 is '1', the timeout has expired and the p/e.c. is erasing the block(s). if the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts, and the device is reset to read array. it is not necessary to program the block with 0000h as the p/e.c. will do this automatically be- fore to erasing to ffffh. read operations after the sixth rising edge of w or e output the status register status bits. during the executionof the erase by the p/e.c., the memory accepts only the erase suspend es and read/reset rd instructions. data polling bit dq7 returns '0' while the erasure is in progress and '1' when it has completed. the toggle bit dq2 and dq6 toggle during the erase operation. they stop when erase is completed. after completion the statusregister bit dq5 returns '1' if there has been an erase failure. in such a situation, the toggle bit dq2 can be used to determine which block is not correctly erased. in the case of erase failure, a read/reset rd instruction is necessaryin order to reset the p/e.c. 11/28 M29F105B
symbol alt parameter test condition M29F105B unit -55 -70 -90 v cc =5v 5% v cc =5v 10% high speed interface standard interface min max min max min max t avav t rc address valid to next address valid e=v il ,g=v il 55 70 90 ns t avqv t acc address valid to output valid e=v il ,g=v il 55 70 90 ns t elqx (1) t lz chip enable low to output transition g=v il 00 ns t elqv (2) t ce chip enable low to output valid g=v il 55 70 90 ns t glqx (1) t olz output enable low to output transition e=v il 00 ns t glqv (2) t oe output enable low to output valid e=v il 20 30 35 ns t ehqx t oh chip enable high to output transition g=v il 00 ns t ehqz (1) t hz chip enable high to output hi-z g=v il 15 20 20 ns t ghqx t oh output enable high to output transition e=v il 00 ns t ghqz (1) t df output enable high to output hi-z e=v il 15 20 20 ns t axqx t oh address transition to output transition e=v il ,g=v il 00 ns notes: 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv -t glqv after the falling edge of e without increasing t elqv . table 14. read ac characteristics (t a = 0 to 70 c or 40 to 85 c) chiperase (ce) instruction. this instructionuses six write cycles. the set-up command 80h is writ- ten to address 555h on the third cycle after the two coded cycles. the chip erase confirm command 10h is similarly written on the sixth cycle after another two coded cycles. if the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts and the device is reset to read array. it is not necessary to program the array with 0000h first as the p/e.c. will auto- matically do this before erasing it to ffffh. read operations after the sixth rising edge of w or e output the status register bits. during the execu- tionof theerase by the p/e.c.,data polling bit dq7 returns '0', then '1' on completion. the toggle bits dq2 and dq6 toggle during erase operation and stop when erase is completed. after completionthe status register bit dq5 returns'1' if there has been an erase failure. 12/28 M29F105B
ai02554 tavav tavqv taxqx telqx tehqx tglqv tglqx tghqx valid a0-a15 e g dq0-dq15 telqv valid address valid and chip enable output enable data valid tehqz tghqz figure 6. read mode ac waveforms note: write enable (w) = high 13/28 M29F105B
symbol alt parameter M29F105B unit -55 -70 -90 v cc =5v 5% v cc =5v 10% high speed interface standard interface min max min max min max t avav t wc address valid to next address valid 55 70 90 ns t elwl t cs chip enable low to write enable low 0 0 0 ns t wlwh t wp write enable low to write enable high 30 35 45 ns t dvwh t ds input valid to write enable high 25 30 45 ns t whdx t dh write enable high to input transition 0 0 0 ns t wheh t ch write enable high to chip enable high 0 0 0 ns t whwl t wph write enable high to write enable low 20 20 20 ns t avwl t as address valid to write enable low 0 0 0 ns t wlax t ah write enable low to address transition 35 45 45 ns t ghwl output enable high to write enable low 000ns t vchel t vcs v cc high to chip enable low 50 50 50 m s t whgl t oeh write enable high to output enable low 000ns table 15. write ac characteristics, write enable controlled (t a = 0 to 70 c or 40 to 85 c) erase suspend (es) instruction. the block erase operation may be suspendedby this instruc- tion which consists of writing the command b0h without any specific address. no coded cycles are required. it permits reading of data from another block and programming in another block while an erase operation is in progress. erase suspend is accepted only during the block erase instruction execution. writing this command during erase timeout will, in addition to suspending the erase, terminate the timeout. the toggle bit dq6 stops toggling when the p/e.c. is suspended.the toggle bits will stop toggling between 0.1 m s and 15 m s after the erase suspend (es) command has been writ- ten. the device will then automatically be set to read memory array mode. when erase is sus- pended, a read from blocks being erased will output dq2 toggling and dq6 at '1'. a read from a block not being erased returns valid data. during suspension the memory will respond only to the erase resume er and the program pg instruc- tions. a program operation can be initiated during erase suspend in one of the blocks not being erased. it will result in both dq2 and dq6 toggling when the data is being programmed.a read/reset command will definitively abort erasure and result in invalid data in the blocks being erased. erase resume (er) instruction. if an erase sus- pend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any coded cycles. 14/28 M29F105B
ai02119 e g w a0-a15 dq0-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl figure 7. write ac waveforms, w controlled note: address are latched on the falling edge of w, data is latched on the rising edge of w. power supply power up the memory command interfaceis reset on power up to read array. either e or w must be tied to v ih during power up to allow maximum security and the possibility to write a command on the first rising edge of e and w. any write cycle initiation is blocked when vcc is below v lko . supply rails normal precautions must be taken for supply volt- age decoupling; each device in a system should have the v cc rail decoupledwith a 0.1 m f capacitor close to the v cc and v ss pins. the pcb trace widths should be sufficient to carry the v cc pro- gram and erase currents required. 15/28 M29F105B
symbol alt parameter M29F105B unit -55 -70 -90 v cc =5v 5% v cc =5v 10% high speed interface standard interface min max min max min max t avav t wc address valid to next address valid 55 70 90 ns t wlel t ws write enable low to chip enable low 000ns t eleh t cp chip enable low to chip enable high 30 35 45 ns t dveh t ds input valid to chip enable high 25 30 45 ns t ehdx t dh chip enable high to input transition 000ns t ehwh t wh chip enable high to write enable high 000ns t ehel t cph chip enable high to chip enable low 20 20 20 ns t avel t as address valid to chip enable low 000ns t elax t ah chip enable low to address transition 35 45 45 ns t ghel output enable high chip enable low 000ns t vchwl t vcs v cc high to write enable low 50 50 50 m s t ehgl t oeh chip enable high to output enable low 000ns table 16. write ac characteristics, chip enable controlled (t a = 0 to 70 c or 40 to 85 c) 16/28 M29F105B
ai02120 e g w a0-a15 dq0-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel figure 8. write ac waveforms, e controlled note: address are latched on the falling edge of e, data is latched on the rising edge of e. 17/28 M29F105B
symbol alt parameter M29F105B unit -55 -70 -90 v cc =5v 5% v cc =5v 10% high speed interface standard interface min max min max min max t whq7v write enable high to dq7 valid (program, w controlled) 10 2400 10 2400 10 2400 m s write enable high to dq7 valid (chip erase, w controlled) 1 30 1 30 1 30 sec t ehq7v chip enable high to dq7 valid (program, e controlled) 10 2400 10 2400 10 2400 m s chip enable high to dq7 valid (chip erase, e controlled) 1 30 1 30 1 30 sec t q7vqv q7 valid to output valid (data polling) 25 30 50 ns t whqv write enable high to output valid (program) 10 2400 10 2400 10 2400 m s write enable high to output valid (chip erase) 1 30 1 30 1 30 sec t ehqv chip enable high to output valid (program) 10 2400 10 2400 10 2400 m s chip enable high to output valid (chip erase) 1 30 1 30 1 30 sec note: 1. all other timings are defined in read ac characteristics table. table 17. data polling and toggle bit ac characteristics (1) (t a = 0 to 70 c or 40 to 85 c) 18/28 M29F105B
ai02121 e g w a0-a15 dq7 ignore valid dq0-dq6/ dq8-dq15 address (within blocks) data output valid tavqv tehq7v tglqv twhq7v valid tq7vqv dq7 data polling (last) cycle memory array read cycle data polling read cycles last write cycle of program or erase instruction telqv figure 9. data polling dq7 ac waveforms 19/28 M29F105B
read dq5 & dq7 at valid address start read dq7 fail pass ai01369 dq7 = data yes no yes no dq5 =1 dq7 = data yes no figure 10. data polling flowchart read dq2, dq5 & dq6 start read dq2, dq6 fail pass ai01873 dq2, dq6 = toggle no no yes yes dq5 =1 no yes dq2, dq6 = toggle figure 11. data toggle flowchart parameter M29F105B unit min typ typical after 100k w/e cycles chip erase (preprogrammed) 0.4 0.6 sec chip erase 1.5 1.7 sec boot block erase 0.6 sec parameter block erase 0.5 sec main block (32kb) erase 0.9 sec main block (64kb) erase 1.0 sec chip program 1.4 1.4 sec word program 20 20 m s program/erase cycles (per block) 100,000 cycles table 18. program, erase times and program, erase endurance cycles (t a = 0 to 70 c; v cc =5v 10% or 5v 5%) 20/28 M29F105B
ai02122 e g w a0-a15 dq6,dq2 tavqv stop toggle last write cycle of program of erase instruction valid valid valid ignore data toggle read cycle memory array read cycle twhqv tehqv telqv tglqv data toggle read cycle dq0-dq1,dq3-dq5,dq7/ dq8-dq15 figure 12. data toggle dq6, dq2 ac waveforms note: all other timings are as a normal read cycle. 21/28 M29F105B
block address on a12, a13, a14, a15 w=v ih ai02250b g, a9 = v id , e=v il n=0 wait 4 m s wait 100 m s w=v il w=v ih g=v ih verify block protection a0, a6 = v il ,a1=v ih and a9 = v id a12-a15 defined block a9 = v ih ++n =25 start fail pass yes no data = 01h yes no a9 = v ih set-up protection verify wait 4 m s wait 60ns e=v il g=v il figure 13. block protection flowchart 22/28 M29F105B
protect all blocks ai02251b data e, g, a9 = v id wait 4 m s w=v ih e, g = v ih wait 10ms = 00h next block w=v il ++n = 1000 start fail yes yes no pass no last blk. yes no n=0 set-up unprotect verify verify block unprotection e=v il ,a0=v il , a1, a6 = v ih and a9 = v id a12-a15 defined block w=v ih wait 4 m s wait 60ns g=v il figure 14. all blocks unprotection flowchart 23/28 M29F105B
write block protect instruction as per oinstructionso table ai02252b n=0 wait 4 m s wait 100 m s w=v il w=v ih wait 4 m s verify block protection a0, a6 = v il ,a1=v ih a12-a15 identify block ++n =25 start fail pass yes no data = 01h yes no set-up protection verify wait 60ns g=v il e=v il g=v ih a6 = v ih a6 = v ih figure 15. block protection flowchart with bp instruction 24/28 M29F105B
protect all blocks ai02253b data write blocks unprotect instruction as per oinstructionso table wait 4 m s w=v ih wait 10ms = 00h next block w=v il ++n = 1000 start yes yes no no last blk. yes no n=0 set-up unprotect verify w=v ih verify block unprotection a0 = v il ; a1, a6 = v ih ; a12-a15 identify block wait 60ns g=v il fail pass wait 4 m s e=v il g=v ih a6 = v ih a6 = v ih figure 16. all blocks unprotecting flowchart with bu instruction 25/28 M29F105B
ordering information scheme devices are shipped from the factory with the memory content erased (to ffh). for a list of available options (speed, package, etc...) or for further informationon any aspect of this device, please contact the stmicroelectronics sales office nearest to you. operating voltage f5v array matrix b bottom boot speed -55 55ns -70 70ns -90 90ns power supplies blank v cc 10% xv cc 5% package n tsop40 10 x 14mm option tr tape & reel packing temp. range 1 0 to 70 c 6 40 to 85 c example: M29F105B -70 x n 1 tr 26/28 M29F105B
tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.05 0.037 0.041 b 0.17 0.27 0.007 0.011 c 0.10 0.21 0.004 0.008 d 13.80 14.20 0.543 0.559 d1 12.30 12.50 0.484 0.492 e 9.90 10.10 0.390 0.398 e 0.50 0.020 l 0.50 0.70 0.020 0.028 a 0 5 0 5 n40 40 cp 0.10 0.004 drawing is not to scale. tsop40 - 40 lead plastic thin small outline, 10 x 14mm 27/28 M29F105B
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. spec ifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? 1998 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. 28/28 M29F105B

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